Shallow trench isolation process

Details Shallow trench isolation process Shallow trench isolation process

1998-04-20

1999-11-23

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438430, 438700, H01L 2176

Patent

active

059899778

ABSTRACT:
The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A thick thermal oxide film is created at and near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

REFERENCES:
patent: 4582565 (1986-04-01), Kawakatsu
patent: 4666556 (1987-05-01), Fulton et al.
patent: 5059550 (1991-10-01), Tateoka et al.
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5116779 (1992-05-01), Iguchi
patent: 5455194 (1995-10-01), Vasquez et al.
patent: 5472904 (1995-12-01), Figura et al.
patent: 5521422 (1996-05-01), Mandelman et al.
patent: 5591681 (1997-01-01), Wristers et al.
patent: 5679601 (1997-10-01), Wu
patent: 5780346 (1998-07-01), Arghavani et al.
Stanley Wolf and Richard N. Tauber "Silicon Processing for the VLSI Era", vol. 1, Process Technology, pp. 25, 187-191, 194, 206-207, 532, 546-551, 581, 1986.
Andres Bryant et al., Characteristics of CMOS Device Isolation for the ULSI Age, 1994 IEEE, pp. 671-674.
Asanga H. Perera et al., Trench Isolation for 0.45 .mu.Active Pitch and Below, 1995 IEEE, pp. 679-682.
O. Joubert et al., Polysilicon Gate Etching in High-Density Plasmas: Comparison Between Oxide Hard Mask and Resist Mask, J. Electrochem. Soc., vol. 144, No. 5, May 1997, pp. 1854-1861.

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