Semiconductor device having circuit element in stress gradient r

Details Semiconductor device having circuit element in stress gradient r Semiconductor device having circuit element in stress gradient r

1997-07-10

1999-03-30

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

257536, 257543, H01L 322, H01L 21265

Patent

active

058893121

ABSTRACT:
A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.

REFERENCES:
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patent: 5065132 (1991-11-01), Taddiken et al.
patent: 5262664 (1993-11-01), Jung-Suk
patent: 5304838 (1994-04-01), Ozawa
Sze, Semiconductor Devices: Physics and Technology, 1985, pp. 6-7.
Miura et al., "Residual Stress Measurement in Silicon Substrates after Thermal Oxidation," Series A, vol. 36, No. 3, Jul. 1993, pp. 302-308.
Stauley wolf, "Fully Recessed Oxide Locos Processes", Silicon Processing for the VLSI Era, vol. II, p. 28, 2.3.

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