Memory cell circuit and array

Details Memory cell circuit and array Memory cell circuit and array

1990-12-31

1994-02-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

36518909, 365233, G11C 1300

Patent

active

052873048

ABSTRACT:
An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).

REFERENCES:
patent: 3611317 (1971-10-01), Bonfeld
patent: 3638202 (1972-01-01), Schroeder
patent: 4184208 (1980-01-01), Tubbs
patent: 4646271 (1987-02-01), Uchiyama
IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug. 1979, "Single V-Groove High Density Static Random-Access Memory Cell", by S. E. Schuster, pp. 1282-1283.

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