Arbiter circuit for establishing priority control of read, write

Details Arbiter circuit for establishing priority control of read, write Arbiter circuit for establishing priority control of read, write

1988-02-26

1990-09-11

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, 365195, 36518907, 36518908, 36523003, G11C 700

Patent

active

049568205

ABSTRACT:
An arbiter circuit providing priority control of dynamic memory operations as a memory access signal control circuit which regulates the order in which dynamic memory access signals, such as read, write and refresh signals, are executed in effecting particular operating functions of a dynamic memory. The arbiter circuit has a first circuit element to temporarily hold a given access signal or signals, a second circuit element to inhibit transfer of any access signal when another access signal is already being executed, a third circuit element to synchronize individual access signals that are generated asynchronously, and a fourth circuit element to reset arbiter circuit upon the end of each access signal. The memory access signals or request signals are queued as necessary according to a priority allocation such that a write request signal heads the priority list, followed by a refresh request signal and a read request signal in order.

REFERENCES:
patent: 4635224 (1987-01-01), Muller
patent: 4757217 (1988-07-01), Sawada et al.
patent: 4758991 (1988-07-01), Ichida
patent: 4780849 (1988-10-01), Nakagawa
Computer Design, vol. 22, Mar. 83, No. 3/Integrated CRTs, "The Chip That Refreshes Itself" by Fallin et al., pp. 111-118.

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