Method of making an interconnect structure employing equivalent

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438669, 438468, 438927, 438957, 438128, 438761, 438385, 438598, 438622, 257773, 257775, 257774, 257536, H01L 2144, H01L 21326, H01L 2182, H01L 2348

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active

059638311

ABSTRACT:
A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

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patent: 5739587 (1998-04-01), Sato
patent: 5789587 (1998-04-01), Sato
patent: 5789783 (1998-08-01), Choundhury et al.

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