Electronic digital logic circuitry – Threshold – With field-effect transistor
Patent
1993-09-20
1996-12-24
Westin, Edward P.
Electronic digital logic circuitry
Threshold
With field-effect transistor
326119, 326 83, H03K 19017
Patent
active
055876684
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device, and in particular, provides a semiconductor integrated circuit device possessing a completely novel architecture in order to realize an ultra-large scale integration and ultra-high function of the semiconductor logical integrated circuit.
BACKGROUND ART
Presently, developments in semiconductor integrated circuit technology are proceeding at an astonishing rate; for example, using the example of dynamic memory, from 4 megabits to 16 megabits are already in production, while the development of ultra-high density memories having a capacity of more than 64 megabits has been completed. In memory chips having a capacity of 64 megabits, in actuality, approximately 120 million MOS transistors are integrated on a silicon chip of at most 1 cm.sup.2. The present astonishing progress in LSI technology has been achieved as a result of progress in microstructurization of elements and in microfabrication technology. Accordingly, semiconductor memories, the capacity of which can be expanded simply by the accumulation on a single chip of a great number of memory cells having identical structures, have been attained at a truly astonishing rate of progress.
However, the record progress attained with regard to memory has been unattainable in the case of logical LSI. It is true that high function CPUs from 16 to 32 bit and 64 bit and various types of high function logical LSI have been developed; however, on the threshold of the ultra LSI era, great problems are being confronted in the design and production of logical LSI.
The first problem is that of how to design such chips. Logical LSI chips are configured logically to construct logic with binary signals having a value of 1 or 0 by means of the combination of the MOS transistors which function as switching elements. In this method, because a large number of transistors must be connected to one another in order to configure simple logical functions, there are problems in that: solve the problem of [1] above, it is necessary to be creative in layout and minimize, as much as possible, wasted surface area.
The design of conventional 8 bit microprocessors and the like was diligently conducted by trained personnel; however, with the increase in scale of logical circuits and the increase in the number of elements, the manual design of such logical circuits requires astronomical amounts of time, that it has become, in practice, impossible. In the case of memory LSI, the possibility of layout design by means simply of the repetitive arrangement in a plane of a great number of patterns of sense amplifiers or memory cells having identical structures as is a point which essentially differs from the case of logical LSI. There has been much research and development in the so-called CAD (Computer Aided Design) field, in which computers are used in the circuitry and layout design of logical LSI; however, the present state of such efforts is such that the degree of integration attainable thereby is greatly inferior to the degree of integration obtainable manually. The CAD is presently in wide use to arrange basic gates, such as AND (logical product), OR (logical sum), or XOR (exclusive logical sum) gates, or flip flops or the like as building blocks on a chip, and connecting these building blocks to one another.
It is certain that the amount of time required for design is shortened; however, an increase in the degree of integration cannot be expected. Furthermore, as a huge number of interconnects connecting element to element run vertically and horizontally, the situation becomes such that the delay in signal propagation in the interconnection determines the operational speed of the logical LSI, and the effort to increase the speed is presented with a number of difficulties. The introduction of multivalued logical circuits is effective in solving the problems presented by the increase in interconnection. This means, in other words, the introduction of circuits having not merely the two possible
REFERENCES:
patent: 4950917 (1990-08-01), Holler et al.
patent: 4951239 (1990-08-01), Andes et al.
patent: 4961002 (1990-10-01), Tam et al.
patent: 4999525 (1991-03-01), Park et al.
patent: 5021693 (1991-06-01), Shima
patent: 5028810 (1991-07-01), Castro et al.
patent: 5258657 (1993-11-01), Shibata
Ohmi Tadahiro
Shibata Tadashi
Sanders Andrew
Westin Edward P.
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