DRAM cell arrangement having dynamic self-amplifying memory cell

Details DRAM cell arrangement having dynamic self-amplifying memory cell DRAM cell arrangement having dynamic self-amplifying memory cell

1998-06-03

2000-04-11

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257331, H01L 2976

Patent

active

060491051

ABSTRACT:
A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as vertical MOS transistors and are arranged one over the other such that they are connected to one another via a common source/drain region. A source/drain region of the memory transistor is connected to a supply voltage line, a source/drain region of the selection transistor is connected to a bitline, and the gate electrode of the selection transistor is connected to a wordline. A diode structure is connected between the common source/drain region and the gate electrode of the memory transistor.

REFERENCES:
patent: 5308778 (1994-05-01), Fitch et al.
"A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs" M. Terauchi et al., pp. 21-22.
IEEE Transactions of Electron Devices, vol. 41, No. 6, Jun. 1994.

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