Method and apparatus for characterized parasitic capacitance bet

Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters

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324676, G01R 2726

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active

059630434

ABSTRACT:
A method and apparatus for characterizing dimensions and parasitic capacitance between integrated-circuit interconnects are disclosed. The apparatus is a test structure including at least two substantially identical oscillators, at least two substantially identical counters, and a pulse generator. Each of the oscillators is connected to an integrated-circuit interconnect. Each of the counters is coupled to a respective oscillator. The pulse generator is utilized to inject a series of fixed-length clock pulses to each of the oscillators such that the parasitic capacitance of the integrated-circuit interconnects can be characterized by the ratio of oscillation periods of the oscillators to parasitic capacitances of the integrated-circuits.

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IEEE Transactions on Election Devices, vol. Ed-30, No. 2, Feb. 1983, "Simple Formulas for Two- and Three-Dimensional Capacitances," T. Sakurai and K. Tamaru.

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