Single transistor ferroelectric memory cell with asymmetrical fe

Details Single transistor ferroelectric memory cell with asymmetrical fe Single transistor ferroelectric memory cell with asymmetrical fe

1997-08-04

1999-10-05

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

365145, H01L 2976

Patent

active

059628847

ABSTRACT:
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.

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