Dynamic random-access memory system with power-up and power-down

Details Dynamic random-access memory system with power-up and power-down Dynamic random-access memory system with power-up and power-down

1988-11-02

1990-02-13

Williams, Jr., Archie E.

Static information storage and retrieval

Read/write circuit

Data refresh

364900, 36493471, 3649453, 3649481, 3649485, 3649505, 3649649, 36496578, G11C 700, G06F 1216

Patent

active

049012835

ABSTRACT:
A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.

REFERENCES:
patent: 4313180 (1982-01-01), Mochizuki et al.
patent: 4316248 (1982-02-01), Retter
patent: 4616346 (1986-10-01), Nakaizumi et al.
patent: 4625296 (1986-11-01), Shriver
patent: 4631701 (1986-12-01), Kappeler
patent: 4701843 (1987-10-01), Cohen
patent: 4754425 (1988-06-01), Bhadriraju

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