Method and system for selectively independently or simultaneousl

Details Method and system for selectively independently or simultaneousl Method and system for selectively independently or simultaneousl

1998-03-25

2000-08-08

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

711103, 711156, 711166, 711168, 713501, 345515, 348423, 348512, 348515, 352 12, 352 20, G06F 1202

Patent

active

061015911

ABSTRACT:
Method, system and computer program product are provided for selectively separately updating multiple system time clocks or synchronously updating the multiple system time clocks (STCs). Separate or simultaneous updating of the system time clocks is attained by selectively adjusting the addresses to the system time clocks in updatable address register fields. A first address value is provided to a first address register associated with a first STC register and a second address value is provided to a second address register associated with a second STC register. Independent updating of the first STC register and the second STC register is performed when the first address value and the second address value are different, while synchronous updating is performed when the first address value and the second address value comprise a common address value. The technique can be extrapolated to any number of clocks to be updated.

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patent: 5668599 (1997-09-01), Cheney et al.
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patent: 5808722 (1998-09-01), Suzuki
"Reconstructive Inverse Quantization of Motion Picture Expert Group Data", IBM Technical Disclosure Bulletin, vol. 39, No. 03, Mar., 1996, pp. 33-37.

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