Multi-port memory device having masking registers

Details Multi-port memory device having masking registers Multi-port memory device having masking registers

1998-01-13

2000-08-08

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711149, 711154, 36518905, 36523005, G06F 1300

Patent

active

061015792

ABSTRACT:
A multi-port RAM (MPRAM) having a SRAM and a DRAM. A global bus is arranged between the DRAM and the SRAM to provide bi-directional transfer of 256-bit data blocks between the SRAM and the DRAM. Two independent input/output ports are coupled to the SRAM to enable a user to write or read data to or from the SRAM and DRAM. Byte masking is provided for each of the ports to mask bytes of data supplied to the MPRAM. A write-per-bit (WPB) mask register is arranged between the ports and the SRAM to prevent unnecessary bits of input data from being written into the SRAM. A byte write enable (BWE) mask register is arranged between the SRAM and the DRAM to prevent unnecessary bytes of data from being transferred from the SRAM to the DRAM. Each of the mask registers may be loaded with mask data from both of the ports concurrently, or from any one of them.

REFERENCES:
patent: 5561781 (1996-10-01), Braceras et al.
patent: 5887272 (1999-03-01), Sartore et al.

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