Signal delay device for use in semiconductor storage device for

Details Signal delay device for use in semiconductor storage device for Signal delay device for use in semiconductor storage device for

1999-01-04

2000-08-08

Phan, Trong

Static information storage and retrieval

Read/write circuit

Signals

365236, G11C 700, G11C 800

Patent

active

061011363

ABSTRACT:
A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory cell array (102) and an output buffer (106). The signal delay device (104) is composed of a plurality of storage circuits (206-0 and 206-1) connected in parallel. Data values are input to selected of the storage circuits (206-0 and 206-1) by input control signals (DSEL0-DSEL1) and output from selected of the storage circuits (206-0 and 206-1) by output control signals (OSEL0-OSEL1). The DSEL0-DSEL1 and OSEL0-OSEL1 signals are generated in response to count signals (OCNT0-OCNT1).

REFERENCES:
patent: 5715211 (1998-02-01), Toda
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 5895482 (1999-04-01), Toda
patent: 5991226 (1999-11-01), Bhullar

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