Semiconductor integrated circuit device with operation in partia

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257351, 257392, 257402, H01L 2701

Patent

active

061005657

ABSTRACT:
MOS devices are formed on a wafer having a thick silicon layer 3a and a thin silicon layer 3b formed on a buried oxide film. The MOS device formed in the thick silicon layer 3a is activated in a partial depletion type mode. Further, the MOS device formed in the thick silicon layer 3b is activated in a perfect depletion type mode. Therefore, a low leakage current and a high-speed operation can be achieved simultaneously. It is thus possible to solve problems that an integrated circuit must be formed by either one of the partial depletion type device and the perfect depletion type device, and the low leakage current and the high-speed operation are hard to come to fruition simultaneously.

REFERENCES:
patent: 3473094 (1969-10-01), Dillon, Jr.
patent: 4665423 (1987-05-01), Akiya
patent: 5463238 (1995-10-01), Takahashi et al.
patent: 5656825 (1997-08-01), Kusumoto et al.
T. Douseki et al., "TP 5.4: A 0.5V SIMOX-MTCMOS Circuit With 200ps Logic Gate," 1996 IEEE International Solid-State Circuits Conference, vol. Thirty-Nine, ISSN 0193-6530, Feb. 8, 9 and 10, 1996, cover page, and pp. 84, 85, 423.

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