Method for providing performance-driven logic optimization in an

Details Method for providing performance-driven logic optimization in an Method for providing performance-driven logic optimization in an

1998-02-11

2000-08-08

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 8, G06F 1750

Patent

active

060995807

ABSTRACT:
A method for optimizing layout design using logical and physical information performs placement, logic optimization and routing and routing estimates concurrently. In one embodiment, circuit elements of the integrated circuit is partitioned into clusters. The clusters are then placed and routed by iterating over an inner-loop and an outer-loop according to cost functions in the placement model which takes into consideration interconnect wiring delays. Iterating over the inner-loop, logic optimization steps improves the cost functions of the layout design. Iterating over the outer-loop, the size of the clusters, hence the granularity of the placement, is refined until the level of individual cells is reached. The present method is especially suited for parallel processing by multiple central processing units accessing a shared memory containing the design data base.

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