Circuit for clamping enable clock in a semiconductor memory devi

Details Circuit for clamping enable clock in a semiconductor memory devi Circuit for clamping enable clock in a semiconductor memory devi

1993-09-23

1995-11-21

Sikes, William L.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365203, 327309, 327534, H03K 508, G11C 700

Patent

active

054693870

ABSTRACT:
A circuit for a clamping an /RAS signal in a DRAM. The bit line pre-charge generator is activated after the set-up of the VBB voltage, so that /RAS signals may be supplied to the chip after the bit line pre-charge voltage (VBLP) has reached the desired level, thereby preventing malfunction of the sense amplifiers. The circuit includes: a VBB sensor for producing VBB set-up signal S1 when a back bias voltage VBB in the semiconductor memory device has reached a desired level; a power-up generator for producing a power-up signal S2 when power in the semiconductor memory device is set-up; a VBLP generator for generating a bit line pre-charge voltage VBLP; a VBLP controller for holding the VBLP voltage to a ground voltage level according to the S1 and S2 signals; a VBLP sensor for generating VBLP set-up signal S3 when the VBLP voltage has reached a desired level; a /RAS pass signal generator for producing a /RAS pass signal S4 according to the S3 and S2 signals; a NOR circuit for controlling the transmission of the /RAS signals according to the S 4 signal.

REFERENCES:
patent: 4933902 (1990-06-01), Yamada et al.
patent: 4964082 (1990-10-01), Sato
patent: 4985869 (1991-01-01), Miyamoto
patent: 5305270 (1994-04-01), Kim

Affiliated with

Also associated with

Rating

Circuit for clamping enable clock in a semiconductor memory devi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for clamping enable clock in a semiconductor memory devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for clamping enable clock in a semiconductor memory devi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1143042