Semiconductor flash memory having page buffer for verifying prog

Static information storage and retrieval – Floating gate – Particular biasing

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36518512, 36518517, G11C 1606

Patent

active

059368900

ABSTRACT:
A semiconductor memory includes a plurality of memory cells being electrically programmed and coupled to word lines and bit lines. A first latch circuit holds data during a programming operation including a verifying step. A second latch circuit generates a result from verifying a programmed memory cell, in response to the data held in the first latch circuit.

REFERENCES:
patent: 5550842 (1996-08-01), Tran
patent: 5581504 (1996-12-01), Chang
patent: 5677556 (1997-10-01), Endoh
Suh, Kang-Deog et al., "A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE International Solid-State Circuits Conference, 1995, pp. 128-129.

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