High-capacitance dynamic random access memory cell having a stor

Details High-capacitance dynamic random access memory cell having a stor High-capacitance dynamic random access memory cell having a stor

1997-07-24

1999-08-10

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257298, 257300, 257303, 257309, 257317, 438253, 438254, 438255, 438256, 438397, 438398, 438399, H01L 2978, H01L 2992

Patent

active

059362731

ABSTRACT:
A semiconductor structure for a DRAM cell having a high capacitance capacitor. The DRAM cell includes a silicon substrate on which a field oxide layer and a transistor having a gate layer and a source/drain region are formed. A contact surface is formed on a surface of the source/drain region. A silicon nitride layer is formed over the gate layer. A thick oxide layer is formed over one part of the silicon nitride layer, at a lateral side of the contact surface. Silicon nitride spacers are formed over opposite lateral sides of the gate layer, the silicon nitride layer, and the thick oxide layer. One of the silicon nitride spacers located adjacent to the contact surface, is shaped in the form of a pointed protrusion. A self-aligned contact insulating layer covers the thick oxide layer and the other silicon nitride spacer, that is located away from the contact surface. This structure defines a jagged surface over at least the contact surface, the pointed protrusion and the silicon nitride layer. A high surface area capacitor structure, including a first conductive layer, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer, is then formed over the jagged surface.

REFERENCES:
patent: 3384474 (1968-05-01), Park et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5386131 (1995-01-01), Sato

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