SOI compact contactless flash memory cell

Details SOI compact contactless flash memory cell SOI compact contactless flash memory cell

1997-01-22

1998-08-18

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257318, 257347, 36518533, H01L 29788

Patent

active

057961425

ABSTRACT:
A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

REFERENCES:
patent: 5075245 (1991-12-01), Woo et al.
patent: 5617351 (1997-04-01), Bertin et al.
"A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology," 1990 IEDM, pp. 90-94.
"A NAND Structured Cell With A New Programming Technology For Highly Reliable 5-V Only Flash EEPROM," 1990 Symposium on VLSI Technology, pp. 129-130.

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