Method for simplifying the manufacture of an interlayer dielectr

Details Method for simplifying the manufacture of an interlayer dielectr Method for simplifying the manufacture of an interlayer dielectr

1996-07-01

1998-08-18

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438787, 438790, 438793, H01L 21441

Patent

active

057958203

ABSTRACT:
A method and apparatus is provided for simplifying the manufacture of an interlayer dielectric where local interconnects are utilized. The invention utilizes a separate LI stack and first contact stack deposition and etch. In the first step, a layer of oxide etch stop and a layer of TEOS oxide are deposited to form a first LI stack. This stack is then contact etched, filled, and polished. A first contact stack is then formed by deposition of a doped silane oxide layer that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop, a second layer of undoped TEOS oxide, and a final layer of doped silane oxide.

REFERENCES:
patent: 5250468 (1993-10-01), Matsuura et al.
patent: 5578524 (1996-11-01), Fukase et al.

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