SOI substrate fabrication

Details SOI substrate fabrication SOI substrate fabrication

1997-01-27

1997-08-19

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 75, H01L 2701, H01L 2712, H01L 310392, H01L 2904

Patent

active

056591926

ABSTRACT:
A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.

REFERENCES:
patent: 4282543 (1981-08-01), Ihara et al.
patent: 4907053 (1990-03-01), Ohmi
patent: 4943837 (1990-07-01), Konishi et al.
patent: 4992846 (1991-02-01), Sakakibara et al.
patent: 5096854 (1992-03-01), Saito et al.

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