Single cell reference scheme for flash memory sensing and progra

Details Single cell reference scheme for flash memory sensing and progra Single cell reference scheme for flash memory sensing and progra

1993-06-28

1995-01-31

Yoo, Do H.

Static information storage and retrieval

Read/write circuit

Testing

36518909, 365218, G11C 1134

Patent

active

053863887

ABSTRACT:
A reference scheme for verifying the erasing and programming in an electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate which employs a plurality of memory cells, each of which contains a floating gate. The reference scheme employs trimmable single cell reference devices for both the erase verify and program verify operations. The threshold voltages of the reference cells are trimmed to a level below (in the case of the erase verify reference cell) or above (in the case of the program verify reference cell) which all memory cells in the array will be considered in a particular program state (i.e., erased or programmed). In the case of the read reference device, a double-cell read referencing device combining the erase and program verify reference cells is described. Although, the double-cell referencing device is preferred, a trimmable read reference device is also taught.

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