Method for etching integrated semiconductor circuits containing

Details Method for etching integrated semiconductor circuits containing Method for etching integrated semiconductor circuits containing

1984-02-17

1984-10-30

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156652, 156657, 1566591, 204192E, 252 791, H01L 21306, B44C 2506, C03C 1500, C23F 102

Patent

active

044798504

ABSTRACT:
A method for etching a double layer semiconductor structure containing metal silicide layers or a metal silicide-polysilicon layer on a silicon substrate through a photoresist mask by means of reactive ion etching wherein dissociation and ionization of reactant gases take place in a plasma, the improvement which comprises:

REFERENCES:
patent: 4411734 (1983-10-01), Maa
patent: 4444617 (1984-04-01), Whitcomb
"Refractory Silicides for Integrated Circuits", J. Vac. Sci. Techol., 17(4), Jul./Aug. 1980; pp. 775-792.
"Tantalum Silicide/Polycrystalline Silicon-High Conductivity Gates for CMOS LSI Applications"; J. Vac. Sci. Technol., 18(2), Mar. 1981; pp. 345 to 348.
"Molybdenum Etching Using CCI.sub.4 /O.sub.2 Mixture Gas"; Japanese Journal of Applied Physics, Jan. 1982; pp. 168 to 172.

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