Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

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365 51, 365188, 365 63, 365 72, 257210, 257208, H01L 2711

Patent

active

054557879

ABSTRACT:
A semiconductor memory device comprises a layout of a plurality of memory cells each including a pair of device regions, a pair of driver transistors respectively formed on the respective device regions of the pair and having gates and drains thereof cross-connected to each other, a pair of transfer transistors respectively formed on the respective device regions of the pair and controlled by a word line, a pair of load devices respectively disposed in the respective driver transistors of the pair, the pair of transfer transistors having a gate layer formed on the pair of device regions; and the word line being formed so as to cross the pair of driver transistors thereabove and being in contact with the gate layer of the pair of transfer transistors. No region is necessary for mask alignment between the word lines and the gate layer, and an area of a memory cell can be reduced.

REFERENCES:
patent: 4780851 (1988-10-01), Kurakami
patent: 4950620 (1990-08-01), Harrington, III
patent: 5241495 (1993-08-01), Sasaki
patent: 5627192 (1993-11-01), Nogami
IEEE Journal of Solid State Circuits, 1992, 27:1490-1496, Goto et al. A 3.3-V 12-na 16-Mb CMOS SRAM.
IEEE Journal of Solid state Circuits, 1992, 27:1497-1503, Matsumiya et al. A 15-ns 16 Mb CMOS SRAM with Interdigitated Bit-Line Architecture.

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