Synchronous semiconductor memory device with redundancy determin

Details Synchronous semiconductor memory device with redundancy determin Synchronous semiconductor memory device with redundancy determin

1998-11-16

2000-01-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, G11C 700

Patent

active

060117354

ABSTRACT:
A redundancy determination circuit receiving an address signal from an address bus outputs a replacement signal when a set address matches the received address. A multiplexer activates any spare activation signal line that activates respective redundant memory arrays provided in the row direction and column direction in a memory bank at a predetermined timing. The redundancy determination circuit can set the address to use a redundant memory array in either the row direction or the column direction. Therefore, the number of redundancy determination circuits can be reduced.

REFERENCES:
patent: 5452251 (1995-09-01), Akaogi
patent: 5487040 (1996-01-01), Sukegawa et al.
patent: 5548555 (1996-08-01), Lee et al.
patent: 5652725 (1997-07-01), Suma et al.
patent: 5798973 (1998-08-01), Satoshi et al.

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