Fuseless memory repair system and method of operation

Details Fuseless memory repair system and method of operation Fuseless memory repair system and method of operation

1998-03-12

2000-01-04

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523003, 365195, 36523008, 371 225, 371 102, 371 103, G11C 700, G11C 2900

Patent

active

060117346

ABSTRACT:
A Built-In Self Test (720) generates a BIST FAIL signal when a failure is detected at a specific address within a memory array (110). The address associated with the failure is stored in a latch (210). During normal operation, the address stored in latch (210) is compared to addresses being currently accesses. A HIT signal is generated when a match occurs. The HIT signal disables selection of the defective row in array (110). A redundant row select signal selects the redundant row (112) to replace the defective row.

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Sawada et al., "Built-In Self-Repair Circuit for High-Density ASMIC", IEEE Custom Integrated Circuits Conference, pp. 26.1.1-26.1.4 (1989).
Tanabe et al., "A 30-ns 64 wMb DRAM with Built-in Self-Test and Self-Repair Function," IEEE Journal of Solid-State Circuits, vol. 27, No. 11 (1992).

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