Method of manufacturing GaAs field effect transistor

Details Method of manufacturing GaAs field effect transistor Method of manufacturing GaAs field effect transistor

1985-07-17

1987-02-24

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29580, 148187, 156646, 156649, 156653, 156657, 1566591, 156662, 357 41, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

046455639

ABSTRACT:
A method of manufacturing of a GaAs FET wherein a gate structure is first formed on a GaAs substrate. The gate structure consists of a conductive gate layer and an insulative layer, which are in lateral contact with each other on the substrate. Each layer is isotropically deposited by a CVD process and later anisotropically etched using a RIE process, whereby it has a specific width of the submicron order reduced to an extent substantially equal to an initially deposited thickness thereof. The high frequency property of the GaAs FET can be improved due to the decrease in width of the gate layer. Ion implantation is performed with the gate structure used as a mask to provide in the substrate source and drain regions which are self-aligned with the gate structure. The drain regions are removed from the gate layer at a distance equal to the width of the insulative layer.

REFERENCES:
patent: 4378627 (1983-04-01), Jambotkar
patent: 4400865 (1983-08-01), Goth et al.
patent: 4455738 (1984-06-01), Houston et al.
IEDM Technical Digest, pp. 718-721; S. Ogura et al.; 1982, "A Half Micron MOSFET Using Double Implanted LDD".
The transactions of the Institute of Electronics and Communications Engineers of Japan, National Meeting of Semiconductor/Material Department, p. 116, "Heat-Resistant Gate N+ Self-Aligned Structured GaAs MESFET", Kozuka et al; Sep. 1983.
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 2; P. J. Tsang et al; Apr., 1982, "Fabrication of High-Performance LDDFET's with Oxide Side-Wall-Spacer Technology", pp. 220-226.
IEEE Electron Device Letters, vol. EDL-5, No. 5, May 1984, pp. 159-161, New York, U.S.; J. Nulmann, et al.: "'2-GHz 150-piW Self-Aligned Si MESFET Logic, Section III; FIG. 2.

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