Apparatus and method for reducing the number of rename registers

Details Apparatus and method for reducing the number of rename registers Apparatus and method for reducing the number of rename registers

1997-10-28

2000-05-09

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 7, 712 8, 712 9, 712 26, 712205, 712206, 712214, 712215, 712238, 712240, G06F 946

Patent

active

060617772

ABSTRACT:
One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

REFERENCES:
patent: 5659721 (1997-08-01), Shen et al.
patent: 5802340 (1998-09-01), Mallick et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5826070 (1998-10-01), Olson et al.
patent: 5872949 (1999-02-01), Kikuta et al.
patent: 5881263 (1999-03-01), York et al.
patent: 5884061 (1999-03-01), Hesson et al.
patent: 5887161 (1999-03-01), Cheong et al.

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