Split write data processing mechanism for memory controllers uti

Details Split write data processing mechanism for memory controllers uti Split write data processing mechanism for memory controllers uti

1997-06-30

2000-05-09

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711154, 711168, 711201, G06F 1200

Patent

active

060617721

ABSTRACT:
A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.

REFERENCES:
patent: 5535345 (1996-07-01), Fisch et al.
patent: 5732244 (1998-03-01), Gujral
patent: 5841598 (1998-11-01), Horiuchi et al.
Hennessy and Patterson, "Computer Architecture A Quantitative Approach," pp. 414-416, Morgan Kaufmann Publishers Inc., 1990.

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