Apparatus and method for separately layering cache and architect

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711146, 711154, G06F 1200, G06F 1300

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active

060617624

ABSTRACT:
Cache and architectural specific functions are layered within a controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable.

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