Programmable shift register

Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory

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377 69, 377 80, 377 81, G06M 300

Patent

active

06061417&

ABSTRACT:
A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length. The mode control circuit is programmable such that the shift register loads an initial operating state, or to implements bi-directional (count up/down) control. Some of the I/O lines of the programmable interconnect circuit are connected to the next-state control circuit. The next-state control circuit includes a sequence circuit, a maximal count circuit and a skip-state circuit, all of which are programmable to utilize the output signals from the flip-flops that are transmitted on the first bus.

REFERENCES:
patent: 5014244 (1991-05-01), Lammerts et al.
patent: 5367551 (1994-11-01), Okumura et al.
patent: 5481749 (1996-01-01), Grondalski
patent: 5589787 (1996-12-01), Odinot
patent: 5761266 (1998-06-01), Watts, Jr.
Hackett and Leach, "Build Better Sequential Circuits", ASIC and EDA, Mar. 1992, pp. 43-49.

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