Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-02-26
2000-01-04
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438648, 438649, 438656, 438664, 438668, H01L 214763, H01L 2144
Patent
active
060109610
ABSTRACT:
Methods of establishing electrical communication with substrate node locations, methods of forming DRAM circuitry, and semiconductor assemblies are described. In one implementation, a contact opening is formed over a substrate node location with which electrical communication is desired. The contact opening has a base over which a refractory metal layer is formed. A refractory metal silicide layer is formed over the refractory metal layer, and the substrate is exposed to conditions effective to convert the refractory metal layer to a refractory metal silicide. In one embodiment, the refractory metal layer and the refractory metal silicide layer are chemical vapor deposited. In another embodiment, the refractory metal silicide layer comprises a silicide of the refractory metal layer. In a preferred implementation, the refractory metal layer comprises titanium and the refractory metal silicide layer comprises titanium silicide. In another implementation, a composite layer is formed over a substrate and comprises an underlying refractory metal and an overlying silicide layer. The composite layer is annealed to react the underlying metal with a silicon-comprising substrate and form a refractory metal silicide of the underlying refractory metal in contact with the overlying silicide layer. The invention can achieve reductions in silicon consumption in the diffusion regions and maintain low source/drain diode leakage.
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patent: 5793111 (1998-08-01), Zamanian
Kim, J.S. et al., "A Triple Level Metallization Technique for Gigabit Scaled DRAMs", VMIC Conference 1996 ISMIC--106/96/0028(c), Jun. 18-20, 1996, pp. 28-33.
Byun, Jeong Soo, "Epitaxial C49-TiSi.sub.2 Formation on (100) Si Substrate Using TiN.sub.x and ITs Electrical Characteristics as a Shallow Contact Metallization", J. Electrochem. Soc., vol. 143, No. 6, Jun. 1996, pp. 1984-1991.
Carlsson, J. R. A. et al., "Effect of Lateral Confinement and Ti Thickness on the C49 to C54 TiSi.sub.2 Phase Transformation in TiN/Ti Bilayers on Si (001)", Macintosh HD/Articles/1997/TiSi.sub.2, Feb. 14, 1997, pp. 1-14.
Benezny Nema
Bowers Charles
Micro)n Technology, Inc.
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