Integrated circuit planarization and fill biasing design method

Details Integrated circuit planarization and fill biasing design method Integrated circuit planarization and fill biasing design method

1998-09-17

2000-09-19

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

438199, 438631, H01L 21338

Patent

active

061210781

ABSTRACT:
An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.

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