Dynamic logic circuit

Details Dynamic logic circuit Dynamic logic circuit

1998-08-07

2000-05-09

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, 326 93, 326 17, 326112, 326119, 326121, H03K 1901, H03K 1900, H03K 19096, H03K 19094

Patent

active

060609109

ABSTRACT:
A high-speed dynamic logic circuit having a high tolerance to noise includes pMOS and nMOS transistors constructing a buffer, which is connected to an internal dynamic node, for driving an output terminal. Only the pMOS transistor, which operates in an evaluation cycle, is connected to the dynamic node. The nMOS transistor is driven by a signal that is the inverse of a precharge signal. A weak latch, or an nMOS transistor of minimum size driven by the dynamic node, is connected to the output terminal as a leakage compensation circuit.

REFERENCES:
patent: 5525916 (1996-06-01), Gu et al.
patent: 5572151 (1996-11-01), Hanawa et al
patent: 5677641 (1997-10-01), Nishio et al.
patent: 5933038 (1999-08-01), Klass
Neil H.E. Weste et al., "Principles of CMOS VLSI Design", Maruzen K.K., pp. 142-144.

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