Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-03-27
2000-09-12
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
G11C 2900
Patent
active
06119249&
ABSTRACT:
A method of testing, in parallel, a memory device including a plurality of memory cells organized into memory blocks, the memory device having a plurality of wired-OR pre-charged differential data line pairs, includes the steps of enabling a predetermined number of memory blocks at a time; writing to and reading as many bits as the predetermined number of enabled memory blocks in parallel; and detecting when both data lines of each of the wired-OR differential pairs are active at a same time, indicating that at least one bad memory cell exists within at least one of the predetermined number of enabled memory blocks. According to another embodiment, a memory device operable in both a normal and a test mode includes a plurality of memory cells organized into a plurality of blocks; at least one wired-OR pre-charged differential data line pair connected to each of the blocks; a block address decoder, the block address decoder enabling one of the plurality of blocks at a time during normal operation and more than one block at a time when the memory device is operating in test mode; and an output buffer for each of the at least one wired-OR differential pairs, the output buffer including a bad cell detector, the bad cell detector causing an output of the buffer to tri-state when a status of a differential pair connected to the buffer is indicative of at least one bad memory cell within at least one of the plurality of enabled blocks.
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Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Hoa T.
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