Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1998-01-29
2000-09-12
Follansbee, John A.
Electrical computers and digital processing systems: processing
Processing control
Branching
712200, 712214, G06F 938
Patent
active
061192201
ABSTRACT:
An apparatus for supplying instructions to a processor has an instruction cache (1) and a branch target buffer (33). The branch target buffer stores instructions in order of execution achievable if a branch instruction is taken. The instructions in the branch target buffer are arranged before a branch predictor (35) makes a prediction whether or not the branch instruction is taken. If the prediction tells that the branch instruction will be taken, the instructions in the branch target buffer are supplied to an instruction decoder (9). If the prediction tells that the branch instruction will not be taken, instructions in the instruction cache are supplied to the instruction decoder.
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Microarchitecture Support for Improving the Performance of Load target Prediction by Chung-Ho Chen & Akida Wu, Apr. 12.
Benson Walter
Follansbee John A.
Kabushiki Kaisha Toshiba
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