Semiconductor integrated circuit with bipolar transistors and MO

Details Semiconductor integrated circuit with bipolar transistors and MO Semiconductor integrated circuit with bipolar transistors and MO

1992-07-21

1993-06-15

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, H01L 2702

Patent

active

052201872

ABSTRACT:
A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

REFERENCES:
patent: 4766475 (1988-08-01), Kawashima
patent: 4783692 (1988-11-01), Uratani
patent: 4868626 (1989-09-01), Nakazato et al.
patent: 5001365 (1991-03-01), Murabayashi et al.
patent: 5059821 (1991-10-01), Murabayashi et al.
Patent Abstracts of Japan, vol. 9, No. 244 (E-346) (1967), Sep. 30, 1985.
Patent Abstracts of Japan, vol. 7, No. 144 (E-183) (1289), Jun. 23, 1983.

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