Split-polysilicon CMOS process incorporating self-aligned silici

Details Split-polysilicon CMOS process incorporating self-aligned silici Split-polysilicon CMOS process incorporating self-aligned silici

1990-02-26

1991-06-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437 57, 357 42, 357 44, H01L 21265, H01L 21336

Patent

active

050213539

ABSTRACT:
An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

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patent: 4745086 (1988-05-01), Parrillo

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