Semiconductor wafer for improved chemical-mechanical polishing o

Details Semiconductor wafer for improved chemical-mechanical polishing o Semiconductor wafer for improved chemical-mechanical polishing o

1996-06-06

1997-10-28

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566441, 1566571, 216 39, 216 88, 216 89, 437924, H01L 21302

Patent

active

056814232

ABSTRACT:
The present invention is a semiconductor wafer, and a method of fabricating the semiconductor wafer, that reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support pillar is positioned in the cavity. In one embodiment, the pillar has a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the pillar substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.

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Blumenstock, K,; Theisen, J.; Pan, P.; Dulak, J.; Ticknor, A.; and Sandwick, T., "Shallow trench isolation for ultra-large-scale integrated devices," J. Vac. Sci. Technol B 12(1): 54-58, Jan./Feb. 1994.

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