Self-initiated self-refresh mode for memory modules

Details Self-initiated self-refresh mode for memory modules Self-initiated self-refresh mode for memory modules

1998-05-20

2000-09-12

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365233, 365239, G11C 700

Patent

active

061187194

ABSTRACT:
A method and apparatus for selectively causing each bank of a number of banks of DRAMs of a DRAM memory card to enter into the self-refresh mode without affecting the operation of any other bank. In the computer system incorporating the SIMM or DIMM type DRAM cards, each bank of memory on each card has a RAS signal specific to that specific bank. One or more CAS signals are supplied across all of the memory banks, on all cards. Thus, each memory bank is accessed separately for a read/write operation by the RAS becoming active before the CAS becomes active; and refresh takes place by the CAS signal becoming active before the RAS signal becomes active. The number of clock cycles or refresh cycles between active RAS signals to each memory bank are counted. If RAS does not become active for N clock or refresh cycles, a signal is provided within each respective memory bank and that memory bank will immediately, or preferably after M additional clock or refresh cycles enter self-refresh mode without affecting the operation of any other bank. At the same time, the memory controller counts cycles of RAS inactivity for each DRAM bank it controls. A signal is also provided to a register to require a double read/write on the next active read/write cycle to that bank, for reactivating that bank from the self-refresh mode when RAS signal specific to that bank becomes active while CAS is inactive.

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