Semiconductor memory device including disturb refresh test circu

Details Semiconductor memory device including disturb refresh test circu Semiconductor memory device including disturb refresh test circu

1998-11-19

2000-09-12

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365222, G11C 700

Patent

active

061187100

ABSTRACT:
In a semiconductor memory device, replacement is possible with a redundant cell in the same or different memory sub array in a mode other than a particular test mode. A redundancy determining circuit inactivates a spare word line enable signal corresponding to a redundant cell when a disturb refresh acceleration mode test is designated. An SWL driver renders a spare word line non-selective in response to the spare word line enable signal. An NWL driver simultaneously activates a plurality of word lines (except a word line corresponding to a defective cell) in response to a word line enable signal output from the redundancy determining circuit.

REFERENCES:
patent: 5381371 (1995-01-01), Haraguchi
"A Flexible Redundancy Technique for High-Density DRAM's", M. Horiguchi et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.

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