Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1998-08-27
2000-12-26
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711105, 711167, 714811, 714812, 714815, 714819, 714821, 714764, 714805, G06F 1216
Patent
active
061674958
ABSTRACT:
A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND) gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.
REFERENCES:
patent: 4164787 (1979-08-01), Aranguren
patent: 5276856 (1994-01-01), Norsworthy et al.
patent: 5615223 (1997-03-01), Carr
patent: 5835957 (1998-11-01), Lin
patent: 5862337 (1999-01-01), Gray
patent: 5920897 (1999-07-01), Jin et al.
patent: 5928372 (1999-07-01), Yoshida
patent: 5966731 (1999-10-01), Barth et al.
Anonymous, "400MHz SLDRAM, 4M.times.16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughout the United States, pp. 1-22.
Anonymous, "Draft Standard for a High-Speed Memory Interface (SyncLink)", Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Keeth Brent
Manning Troy A.
Cabeca John W.
Chace Christian P.
Micro)n Technology, Inc.
LandOfFree
Method and apparatus for detecting an initialization signal and does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for detecting an initialization signal and , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for detecting an initialization signal and will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1006596