Emulator and corresponding trace control method

Details Emulator and corresponding trace control method Emulator and corresponding trace control method

1996-12-10

2000-04-25

Ellis, Richard L.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 39, 712227, G06F 1130

Patent

active

06055651&

ABSTRACT:
A trace memory in the emulator is formed into a plurality of memory banks. Data to be traced is in principle stored sequentially in each memory bank. A trace condition setting circuit (trace registers) and a trace condition agreement detecting circuit (comparators) are provided to generate a valid/invalid flag FB indicating whether or not the data meet the set condition. This flag FB is stored along with the trace data in each memory bank.

REFERENCES:
patent: 4480317 (1984-10-01), Haag et al.
patent: 4636940 (1987-01-01), Goodwin, Jr.
patent: 4835675 (1989-05-01), Kawai
patent: 5345580 (1994-09-01), Tamaru et al.
patent: 5347649 (1994-09-01), Alderson
patent: 5513317 (1996-04-01), Borchardt et al.
patent: 5715435 (1998-02-01), Ikei
LSI Handbook, edited by Institute of Electronics, Information and Communication Engineers, published by Ohm, Ltd.
IBM Technical Disclosure Bulletin, Tailorable Embedded Event Trace, vol. 34, No. 7B, Dec. 1991, pp. 259-261.
IBM Technical Disclosure Bulletin, Comparator Logic to Assist Trace Facility for ROS Programs, vol. 26, No. 3B, Aug., 1983, pp. 1566-1567.

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