Pipeline memory access using DRAM with multiple independent bank

Details Pipeline memory access using DRAM with multiple independent bank Pipeline memory access using DRAM with multiple independent bank

1997-01-31

2000-04-25

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711 5, 711168, 711167, G06F 1200

Patent

active

060556153

ABSTRACT:
A memory system using at least one DRAM chip and equipped with an interface for transferring input/output data in a packet format includes a plurality of banks within each of the at least one DRAM chip. The memory system further includes a control circuit for accessing a bank for data transfer of a given packet when the bank is different from a previous bank accessed for an immediately preceding packet, and for waiting for an operation to complete in the bank when the bank is the same as the previous bank.

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patent: 4633434 (1986-12-01), Scheuneman
patent: 4680730 (1987-07-01), Omoda et al.
patent: 5060145 (1991-10-01), Scheuneman
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5410670 (1995-04-01), Hansen et al.
patent: 5737563 (1998-04-01), Shigeeda
patent: 5745118 (1998-04-01), Alcorn et al.
patent: 5748914 (1998-05-01), Barth et al.
patent: 5768559 (1998-06-01), Lino et al.

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