Zoom in pin nest structure, test vehicle having the...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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C438S018000

Reexamination Certificate

active

07154115

ABSTRACT:
A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.

REFERENCES:
patent: 5977558 (1999-11-01), Lee
patent: 6268717 (2001-07-01), Jarvis et al.
patent: 6362634 (2002-03-01), Jarvis et al.
Integrated Circuit Yield Management and Yield Analysis: Development and Implementation; Charles H. Stapper et al.; IEEE Transactions on Semiconductor Manufacturing; vol. 8, No. 2, May 1995; pp. 95-102.
Extraction of Defect Size Distributions in an IC Layer Using Test Structure Data; Jitendra B. Khare et al.; IEEE Transactions on Semiconductor Manufacturing, vol. 7, No. 3, Aug. 1994; pp. 354-368.
Defect Size Distribution In VLSI Chips; Reinhard Glang; IEEE Transactions on Semiconductor Manufacturing, vol. 4, No. 4, Nov. 1991; pp. 265-269.

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