Zone-segregated circuit for the testing of electrically programm

Details Zone-segregated circuit for the testing of electrically programm Zone-segregated circuit for the testing of electrically programm

1991-06-21

1994-03-01

Lee, Benny

Static information storage and retrieval

Read/write circuit

Testing

371 211, 365 63, G11C 2900

Patent

active

052914488

ABSTRACT:
To reduce the number of connections in an electrically programmable memory circuit, a device for the testing of the memory cells is proposed. The test consists in the reading of the current that goes through the cells to which access is had in reading mode. The testing device no longer uses specific testing connections between the cells and the corresponding input/output pins but the operational connections of the reading mode, between the reading amplifiers and the input/output buffers, in short-circuiting the input and the output of the reading amplifiers located in a zone close to the memory cells and the input/output buffers located on the peripheral zone, close to the input/output pins. The means to short-circuit the amplifiers and the buffers are respectively located in a zone close to the memory cells, and in the peripheral zone.

REFERENCES:
patent: 5157627 (1992-10-01), Gheewala
Gastaldi et al, "A 1-Mbit CMOS EPROM with Enhanced Verification", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1150-1156, (Oct. 1988).

Affiliated with

Also associated with

Rating

Zone-segregated circuit for the testing of electrically programm does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Zone-segregated circuit for the testing of electrically programm, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Zone-segregated circuit for the testing of electrically programm will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-584103