Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-12-18
2003-06-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C326S093000, C327S208000
Reexamination Certificate
active
06580294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to semiconductor circuits. More particularly, the invention relates to differential domino logic stages for digital adders.
2. Discussion
Fundamental to the operation of virtually all digital microprocessors is the function of digital (i.e., binary) addition. Addition is used not only to provide numerical sums, but also in the implementation of numerous logic functions. In a typical microprocessor, many adders are used for these functions. When two digital words are added, the carry bit that results from the addition of lessor significant bits must be considered when adding more significant bits. The carry bit can easily be considered by rippling a carry signal through the entire addition chain as the addition is performed. A problem with such an approach, particularly for relatively large words (e.g., 64 bits) is that substantial time is required to ripple the carry signal. Since adders are often performing logic functions in critical time paths, the time needed to ripple the carry signal can slow up the microprocessor.
In response to the above concerns, techniques such as the static carry look-ahead (CLA) adder described in U.S. Pat. No. 5,847,984 to Mahurin have evolved. A difficulty associated with such a static adder, however, is that there typically is relatively high input loading on the circuit. High input loads can compromise speed. Domino circuits use clock signals to dynamically obtain “precharge” and “evaluation” phases for the domino circuits. These phases enable a reduction in input loading resulting in higher gain per stage and considerable speed increases. Two types of domino circuits are single ended and differential circuits. Single ended domino circuits use fewer transistors than the equivalent evaluate circuits, but require two stages of logic when constructing exclusive OR (XOR) gates. This characteristic can be important considering the fact that XOR gates are used in the fabrication of arithmetic logic units (ALUs). Domino circuits such as the p-type polysilicon (or metal oxide) semiconductor (PMOS) circuit
10
of FIG.
3
and the n-type polysilicon (or metal oxide) semiconductor (NMOS) circuit
12
of
FIG. 4
, on the other hand, are commonly referred to as differential domino circuits, and are more robust and faster than single ended domino circuits. An important characteristic of differential domino circuits is that they lend themselves to the implementation of XOR gates with one stage of logic.
Traditionally, each differential domino logic stage has a precharge circuit
14
, a first evaluate circuit
16
and a second evaluate circuit
18
. The precharge circuit
14
is connected to a first potential
20
and a differential output defined by a first output node
22
and a second output node
24
. The first evaluate circuit
16
is connected to a second potential
26
and the first output node
22
. The second evaluate circuit
18
is connected to the second potential
26
and the second output node
24
. It is important to note that the first (or “true”) evaluate circuit
16
and the second (or “not true”) evaluate circuit
18
are not symmetric under the conventional approach. Simply put, input transistor T
1
is in parallel with the transistor stack T
2
/T
3
, whereas input transistor T
4
is not in parallel with the transistor stack T
5
/T
6
. This is because in an adder the first evaluate circuit
16
implements the expression g
1
+p
1
g
0
, whereas the second evaluate circuit
18
implements the expression g
1n
(p
1n
+g
0n
). Such an asymmetrical architecture can be more difficult to fabricate and does not allow the g
on
transistor (T
6
) to be connected directly to the output node.
REFERENCES:
patent: 5384493 (1995-01-01), Furuki
patent: 5777491 (1998-07-01), Hwang et al.
patent: 5847984 (1998-12-01), Mahurin
patent: 6133761 (2000-10-01), Matsubara
patent: 6205463 (2001-03-01), Manglore et al.
patent: 6316960 (2001-11-01), Ye
Intel Corporation
Tan Vibol
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