Zig-zag SPS CCD memory

Details Zig-zag SPS CCD memory Zig-zag SPS CCD memory

1976-10-29

1978-07-25

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Sipo/piso

307221D, 357 24, 365183, G11C 1928, G11C 1134, G11C 900

Patent

active

041033477

ABSTRACT:
A CCD memory is comprised of an array of serial-parallel-serial memory blocks. Each block is comprised of an N-stage serial-parallel register, an M-stage stack, and an N-stage parallel-serial register. The serial-parallel register has N outputs which couple in parallel to N inputs of the stack. The parallel-serial register has N inputs which couple in parallel to N outputs of the stack. Both registers have a zig-zag shaped charge transfer path which reduces their linear dimension, and also reduces the width of the stack.

REFERENCES:
patent: 3789240 (1974-01-01), Weimer
patent: 3953837 (1976-04-01), Cheek
patent: 3967254 (1976-06-01), Kosonocky et al.
patent: 4024509 (1977-05-01), Elmer
Sangster, Integrated bucket-brigade delay line using MOS tetrodes, Philips Technical Review, 1970, vol. 31, pp. 266 & 283.
Osamu Ohtsuki et al., CCD with Meander Channel, The Technology and Applications of Charge Coupled Devices, 3rd International Conference, University of Edinburgh, 9/76, pp. 38-43.

Affiliated with

Also associated with

Rating

Zig-zag SPS CCD memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Zig-zag SPS CCD memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Zig-zag SPS CCD memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1425400