Zero Threshold Voltage pFET and method of making same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S288000, C257S339000, C257S345000, C257S316000, C257S408000, C438S286000

Reexamination Certificate

active

06825530

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductors. More particularly, the present invention is directed to a zero threshold voltage pFET and a method of making the same.
2. Background of the Invention
Zero, or low, threshold voltage (ZVt) devices are useful in various types of integrated circuits (ICs). For example, ZVt field-effect transistors (FETs) are desirable in certain applications because of their high switching speed and low saturation voltage. ZVt FETs are useful in analog circuits, e.g., amplifiers and power supplies, and in digital circuits, e.g., for power supply decoupling in logic circuits, among other uses.
In the manufacture of semiconductor ICs, processing often begins with a p-doped wafer. Due to this p-doping, it is a relatively simple matter to form ZVt nFETs without the need to provide any masks in addition to the masks used to form the implanted wells of standard threshold voltage (Std-Vt) FETs. Since there are no additional costs needed for additional masks with respect to ZVt nFETs, Zvt nFETs may be called “free” devices. However, using conventional processing techniques, ZVt pFETs are not free devices, since they would have to be made using an additional counterdoping mask that would not be needed to form the n-well of a Std-Vt pFET. This is illustrated in
FIGS. 1 and 2
.
FIG. 1
illustrates the step of forming a conventional n-well
20
in a p-type substrate
24
using a typical n-well mask
28
. After n-well
20
is formed, a Std-Vt pFET
32
may be made by forming shallow trench isolators (STIs)
36
, gate insulator
40
, gate
44
, source
48
, and drain
52
, among other things, using conventional techniques.
As shown in
FIG. 2
, if a ZVt pFET
56
were desired under conventional thinking, n-well
20
of
FIG. 1
would have to be counterdoped to form a counterdoped region
60
beneath gate
44
′ that would become the channel of the ZVt PFET. After the counterdoping has been performed, the other structures of ZVt pFET
56
, e.g., shallow trench isolators (STIs)
36
′, gate insulator
40
′, gate
44
′, source
48
′, and drain
52
′, among other things, may be formed using conventional techniques. This counterdoping of n-well
20
requires an additional mask
64
to mask regions of substrate
24
where counterdoping is unwanted, e.g., at all regions other than the regions of the ZVt pFETs. This additional mask
64
and associated wafer processing adds to the cost of an IC. Due to these additional costs, ZVt pFETs are not free devices. Since ZVt pFETs are not free devices, IC designers generally avoid using them. It would be beneficial if there were a method of making ZVt pFETs without additional mask and associated processing costs.
SUMMARY OF INVENTION
An integrated circuit comprising a device that includes a substrate made of a material. The substrate includes a surface, an implanted well having a first dopant type and a lower portion distal from the surface. A pocket consisting of the material is formed within the implanted well between the lower portion of the implanted well and the surface of the substrate. An insulator is located proximate the surface of the substrate above the pocket. An electrode is located proximate the insulator and is located substantially in registration with the pocket.
A method of forming an integrated circuit device on a substrate made of a material and having a surface. The method comprises the step of providing a mask to the substrate that protects a pocket of the adjacent the surface of the substrate. An implanted well is formed so that the implanted well isolates the pocket. An insulator is formed proximate the surface of the substrate above the pocket. An electrode is formed proximate the insulator above the pocket.


REFERENCES:
patent: 5773863 (1998-06-01), Burr et al.
patent: 5780912 (1998-07-01), Burr et al.
patent: 5985727 (1999-11-01), Burr
patent: 6093951 (2000-07-01), Burr
patent: 6110783 (2000-08-01), Burr
patent: 6121666 (2000-09-01), Burr
patent: 6489224 (2002-12-01), Burr
patent: 6566204 (2003-05-01), Wang et al.
patent: 6624455 (2003-09-01), Miyanaga et al.
patent: 2000150668 (2000-05-01), None

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