Zero static power memory device redundancy circuitry

Details Zero static power memory device redundancy circuitry Zero static power memory device redundancy circuitry

1994-08-17

1995-10-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

054576563

ABSTRACT:
A memory redundancy apparatus for replacing defective memory cells in a main memory cell array of a memory device is disclosed. The memory redundancy apparatus operates between two electric potential representing two logic states, and receives a plurality of decoded address signals generated by an input decoding logic to selectively access the redundant memory cells. The memory redundancy apparatus comprises a programmable redundancy decoder logic that receives the address signals and selectively accesses the redundant memory cells to replace the defective memory cells. The memory redundancy apparatus further comprises a redundancy activation circuit coupled to and outputs an activation signal to the programmable redundancy decoder logic so as to activate the operation of the programmable redundancy decoder logic. The disclosed memory redundancy apparatus is capable of zero power consumption when not activated, and the fuse elements necessary to be programmed are relatively few in number.

REFERENCES:
patent: 5379258 (1995-01-01), Murakami et al.

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